1. Field of the Invention
This invention is related to the field of processors and, more particularly, to generating addresses in processors.
2. Description of the Related Art
The x86 architecture (also known as the IA-32 architecture) has enjoyed widespread acceptance and success in the marketplace. Accordingly, it is advantageous to design processors according to the x86 architecture. Such processors may benefit from the large body of software written to the x86 architecture (since such processors may execute the software and thus computer systems employing the processors may enjoy increased acceptance in the market due to the large amount of available software).
As computer systems have continued to evolve, 64 bit address size (and sometimes operand size) has become desirable. A larger address size allows for programs having a larger memory footprint (the amount of memory occupied by the instructions in the program and the data operated upon by the program) to operate within the memory space. A larger operand size allows for operating upon larger operands, or for more precision in operands. More powerful applications and/or operating systems may be possible using 64 bit address and/or operand sizes.
Unfortunately, the x86 architecture is limited to a maximum 32 bit operand size and 32 bit address size. The operand size refers to the number of bits operated upon by the processor (e.g. the number of bits in a source or destination operand). The address size refers to the number of bits in an address generated by the processor. Thus, processors employing the x86 architecture may not serve the needs of applications which may benefit from 64 bit address or operand sizes.
The x86 architecture can operate using a segmented memory model. When using address sizes of 64 bits, however, a flat memory model may be desirable. The process of generating virtual addresses in a flat memory model can differ from the process of generating virtual addresses in a segmented memory model. Accordingly, for a processor to be able to operate using a flat memory model and a segmented memory model, it must be able to generate virtual addresses for either type of model. It would be desirable for a processor to be able to generate virtual addresses for either a flat memory model or a segmented memory model using existing address generation techniques.
The problems outlined above are in large part solved by an apparatus and method for generating virtual addresses for different types of memory models using an existing address generation unit. A processor can be configured to operate using either a segmented memory model or a flat memory model according to an operating mode. When the processor is operating using a segmented memory model, it can use the base address of a segment register to calculate a virtual address. When the processor is operating using a flat memory model, it can use the base address of a pseudo segment register to calculate a virtual address. In one embodiment, this base address can be zero. In this manner, the processor can use existing address generation techniques to generate a virtual address for either a segmented memory model or a flat memory model. More particularly, a segment register and a pseudo segment register can be located in a register file such that a processor can read a value from the register file to perform address generation regardless of the operating mode.
In one embodiment, a processor can include a segment register that stores a segment descriptor and a pseudo segment register that stores a base address. The segment descriptor includes a base address, a first operating mode indication, and a second operating mode indication. The first and second operating mode indications can be used by the processor along with an enable indication in a control register to establish an operating mode. The operating mode can indicate whether the processor is currently using a segmented memory model or a flat memory model. If the processor is using a segmented memory model, it can convey the base address from the segment register to an address generation unit to generate a virtual address. If the processor is using a flat memory model, it can convey the base address from the pseudo segment register to the address generation unit to generate a virtual address.
The use of the apparatus and method described herein may advantageously allow a processor to generate virtual addresses for either a segmented memory model or a flat memory model using existing address generation techniques.